H.264 Deblock Function Engine (DFE) Core v.1.0 is designed for post processing applied to the video sequences.
It can be used in the H.264 hardware accelerator applications (FPGA) that require real time processing.
Application
video surveillance;
video conferences;
video broadcasting;
digital video playback.
The Deblock filter embbeded in the core makes block edges more smooth, thus improving the appearance of decoded
images (particularly at higher compression ratios). The other thing is that the filtered macroblock is used
for motion-compensated prediction of further frames in the encoder, resulting in a smaller residual after prediction.
Features
Supports requirements of ISO/IEC 14496-10 standard up to High Profile at Level 4.2
Frame, Field or MBAFF processing
Supports up to 500,000 Macroblocks/s operation
4:2:0 supported
Example Implementaiton Statistics
Family
Example Device
Fmax (MHz)
Slices1/ LUT- FF2
IOB3
GCLK
BRAM
MULT/ DSP48
DCM/ CMT
Design Tools
Spartan-3x™
XC3xSxxxx-x
50
1515
507
1
13
0
1
ISE 9.1.01i
Virtex-4™
XC4VxXxxx-x
120
1522
507
1
13
0
1
ISE 9.1.01i
Virtex-5™
XC5VxXxxx-x
180
2136
507
1
13
0
1
ISE 9.1.01i
Notes:
Actual slice count dependent on percentage of unrelated logic - see Mapping Report File for details.
Slices not reported for Virtex-5, so LUT-FF is used instead.
Assuming all core I/Os and clocks are routed off-chip.
Diagram
The diagram below shows the Deblock Function Engine IP Core (DFE IP Core) and some optional external
(external to DFE block) functional blocks that are necessary for DFE block operating.
Note:
To see diagram captions you should have Java script enabled.
For technical queries and more information request, contact us.
Purchasing info
H.264 Deblock Function Engine (DFE) Core can be supplied as a NetList(EDIF) or VHDL-source code along with test benches on C- reference code.
